The present invention generally relates to a method for forming solder bumps for a flip-chip bonding process and structures formed and more particularly, relates to a method for forming solder bumps that have substantially the same height for flip-chip bonding wherein a gap for flowing an underfill material in-between a chip and a substrate is increased to reduce fill time and structures formed by the method.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique.
For instance, in a conventional thin film electrodeposition process for depositing solder bumps, bond pads are first formed on a top surface of a substrate for making electrical connections to the outside circuits. The bond pads are normally formed of a conductive metal such as aluminum. The bond pads may be passivated in a passivation layer with windows opened by a photolithography process to allow electrical connections to be made to the bond pads. The passivation layer may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer is applied on top of the semiconductor device to provide both planarization and physical protection of the circuits formed on the device. Onto a top surface of the passivation layer and an exposed top surface of the bond pads, is then deposited an under bump metallurgy (UBM) layer. The under bump metallurgy layer normally consists of an adhesion/diffusion barrier layer and a wetting layer. The adhesion/diffusion barrier layer may be formed of Ti, TiN or other metal such as Cr. The wetting layer is normally formed of a Cu layer or a Ni layer. The UBM layer improves bonding between a solder ball to be formed and the top surface of the bond pads.
In the next step of the process, a photoresist layer is deposited on top of the UBM layer and patterned to define window openings for the solder balls to be subsequently formed. In the following electrodeposition process, solder balls are electro-deposited into window openings forming a structure protruding from the top surface of the photoresist layer. The use of the photoresist layer must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, or preferably a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used so that high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process achieved. To maintain high accuracy in the imaging process on the photoresist layer, reasonably thin photoresist layer must be used resulting in a mushroom configuration of the solder bump deposited therein. The mushroom shape of the solder bump contributes to the inability of a conventional process in producing fine-pitched solder bumps.
The photoresist layer is then removed in a wet stripping process. The mushroom-shaped solder bump remains while the UBM layer is also intact. In the next step of the process, the UBM layer is etched away by using the solder bumps as a mask in a wet etching process. The solder bumps are then heated in a reflow process to form solder balls. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide a larger number of input/output terminals than that possible from a conventional quad flat package.
In a typical micro-BGA package, a flexible interposer or underfill layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 xcexcm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 xcexcm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
The conventional method for depositing solder bumps described above utilizing solder masks presents a number of processing difficulties. For instance, one of the difficulties is the possible misalignment of a solder mask used during a solder bump deposition process. This is shown in FIGS. 1 and 3. For instance, FIGS. 1A and 1B illustrate a conventional solder masking process that does not have a solder mask misalignment problem. When a solder mask 10 is positioned on a semiconductor substrate 20 which has a metal trace 22 and a bond pad 24 formed on a top surface, an opening 12 in the solder mask 10 should be aligned with the bond pad 24. Under an ideal processing condition shown in FIGS. 1A and 1B, the opening 12 is perfectly aligned with the bond pad 24 and the metal trace 22 and thus, a ball-limiting-metallurgy (BLM) layer (not shown) deposited on the bond pad 24 limits the reflow of a solder bump (not shown) into a perfectly shaped solder ball 30 which covers entirely the bond pad 24.
However, under normal fabrication conditions, the solder mask 10 is frequently misaligned to the semiconductor substrate 20 resulting in defectively formed solder balls 30, as shown in FIGS. 1D and 1F. For instance, in FIGS. 1C and 1D, solder mask 10 is misaligned to the semiconductor substrate 20 since mask 10 is positioned too far to the right of the bond pad 24. After a solder bump (not shown) is deposited into the opening 12 in the mask 10, an unusually tall solder ball 30 is formed due to the fact that only a partial surface area of the bond pad 24 is covered so that there is insufficient bond pad area for the solder ball to spread out and assume its normal height. This is shown in FIG. 1D.
In another occurrence of misalignment, as shown in FIGS. 1E and 1F, the solder mask 10 is positioned too far to the left in relation to the bond pad 24 such that both the bond pad 24 and the metal trace 22 are covered by a solder bump subsequently deposited into the opening 12. After a solder reflow process, a solder ball 30 is formed, as shown in FIG. IF, with a smaller height since the ball covers a larger surface area (i.e. covers a BLM layer) and not only the bond pad area.
The detrimental effect of a misalignment between the solder mask 10 and the semiconductor substrate 20 is shown in FIGS. 3A and 3B. For instance, FIG. 3A illustrates that the solder mask 10 with openings 12 provided therein overlaps a plurality of bond pads 24 and metal traces 22. The center bond pad 24 is only partially covered by the opening 12, while bond pad 24 on the two ends are covered by the opening 12 together with a portion of the metal trace 22. As a result, solder balls 32 of smaller than normal height and solder ball 34 of larger than normal height are produced, as shown in FIG. 3B, after a solder reflow process. After an integrated circuit chip (or die) 40 with bond pads 42 formed thereon is positioned over the semiconductor substrate 20 which has the solder balls 32,34 formed thereon, the solder ball 34 which has the larger height contacts the bond pad 42 while the solder balls 32 which has the smaller height are unable to make contact with the bond pads 42. The bonding defect can thus lead to serious quality and reliability problems in the semiconductor package formed by the IC die 40 and the semiconductor substrate 20.
Another processing difficulty encountered in a conventional solder bump formation process that utilizes solder masks is the formation of voids in-between the solder balls and the solder mask. Furthermore, the rate of filling a gap between an IC die and a semiconductor substrate with an underfill material is also reduced. FIG. 2 illustrates the problem wherein a solder mask 10 with openings 12 formed therein is used. It is seen that, while solder balls 30 bond satisfactorily with the bond pads 42, the opening 12 between the solder balls 30 and the mask 10 is very small. This leads to a flow problem for a subsequently filled underfill material which is unable to completely fill the gap, leading to the formation of voids in the gap. Moreover, a gap 14 of very small size is formed in-between the IC die 40 and the semiconductor substrate 20 due to the presence of the solder mask 10 that remained on top of the semiconductor substrate 20 after the solder reflow process. Since a wet stripping process is usually time consuming and costly, a solder mask 10 that is formed of an insulating material is usually left in a package. The small gap 14 formed in-between the die 40 and the substrate 20 therefore limits the filling rate of an underfill material during a final underfill process.
It is therefore an object of the present invention to provide a method for forming solder bumps for flip-chip bonding that does not have the drawbacks or shortcomings of the conventional solder bump forming process.
It is another object of the present invention to provide a method for forming solder bumps for flip-chip bonding that allows a solder mask to be left in a bonded package without the usual processing problem caused by the presence of the solder mask.
It is a further object of the present invention to provide a method for forming solder bumps for flip-chip bonding without utilizing a solder mask with openings therein for forming the solder bumps.
It is another further object of the present invention to provide a method for forming solder bumps for flip-chip bonding by utilizing a solder mask that has a specifically designed configuration and a small surface area.
It is still another object of the present invention to provide a method for forming solder bumps for flip-chip bonding that allows the formation of solder balls of substantially the same height.
It is yet another object of the present invention to provide a method for forming solder bumps for flip-chip bonding which produces a package having a large gap therein to allow rapid filling of an underfill material.
It is still another further object of the present invention to provide an electronic package that includes a semiconductor substrate, an IC chip, a plurality of solder balls bonding the IC chip to the semiconductor substrate, and a plurality of solder non-wettable masks situated in-between the plurality of solder balls wherein a total volume occupied by the plurality of solder non-wettable masks is less than 50% of the total volume of the gap formed between the semiconductor substrate and the IC chip.
It is yet another further object of the present invention to provide an electronic package that includes a semiconductor substrate, an IC chip, a plurality of solder balls each having substantially the same height for bonding the IC chip to the semiconductor substrate, and a plurality of solder non-wettable masks situated in-between the plurality of solder balls.
In accordance with the present invention, a method for forming solder bumps for flip-chip bonding and structures formed by the method are provided.
In a preferred embodiment, a method for forming solder bumps of uniform height can be carried out by the operating steps of providing a pre-processed semiconductor substrate that has a plurality of metal traces formed on top; depositing at least two solder non-wettable masking strips on top of and perpendicular to the plurality of metal traces, the at least two solder non-wettable masking strips are deposited spaced-apart at a predetermined spacing sufficient for forming a bond pad therein between on the plurality of metal traces; and depositing a solder material onto the bond pad forming solder bumps.
In the method for forming solder bumps of uniform height, the pre-processed semiconductor substrate may be an integrated circuit chip, or a printed circuit board. The method may further include the step of forming at an extreme end of the plurality of metal traces a bond pad, or the step of depositing ball-limiting-metallurgy layers on the bond pad. The method may further include the step of depositing the at least two solder non-wettable masking strips in a material selected from the group consisting of thermally cured epoxies and UV cured acrylates, or the step of depositing the at least two solder non-wettable masking strips by a technique selected from the group consisting of stencil printing, dry film laminating and liquid photo-imageable coating. The method may further include the step of depositing the solder material onto the bond pad by a technique selected from the group consisting of solder dipping, electrodeposition, electroless deposition and stencil printing.
The method for forming solder bumps of uniform height may further include the steps of reflowing the solder bumps into solder balls; bonding the solder balls to conductive pads on an opposite surface of a second semiconductor substrate; and filling a gap between the first and the second semiconductor substrates with an underfill material. The method may further include the step of keeping the at least two solder non-wettable masking strips in the semiconductor substrate such that a gap formed between the first and the second semiconductor substrate is increased.
The present invention is further directed to an electronic package that includes a semiconductor substrate; an IC chip; a plurality of solder balls bonding the IC chip to the semiconductor substrate; a plurality of solder non-wettable masking strips situated in-between the plurality of solder balls, a total volume of the plurality of solder non-wettable masking strips being less than 50% of the total volume of a gap formed between the semiconductor substrate and the IC chip; and an underfill material filling the gap between the semiconductor substrate and the IC chip.
In the electronic package, the package may further include a plurality of conductive traces formed on a top surface of the semiconductor substrate, the plurality of conductive traces may be formed of copper or aluminum. The layer of solder non-wettable masking strips may be selected from the group consisting of thermally cured epoxies and UV curable acrylates. The underfill material may be selected from the group consisting of polyimide, silicon adhesive and epoxy. The electronic package may be a flip-chip package. The layer of solder non-wettable masking strips situated in-between the plurality of solder balls may be formed of elongated strips overlapping partially the plurality of conductive traces formed on either the semiconductor substrate or on the IC chip. The plurality of solder balls may have substantially the same height.